The present invention relates generally to an improved metal silicon field effect transistor (MESFET) and method for fabricating that device, and more particularly to a TiW/Si (titantum-tungsten/silicon) gate for GaAs (gallium arsenide) MESFETs.
A widely used field effect transistor in digital logic circuits is the GaAs MESFET. However, a major difficulty with the use of GaAs MESFETs in digital logic circuits as enhancement-mode field effect transistors (E-MESFETs) is the substantial gate-source and gate-drain parasitic resistances inherent in the conventional design. The sheet resistivity of the ungated portion of GaAs E-MESFET channel is approximately 13 k.OMEGA./.quadrature.. Because of misregistration tolerances necessary for alignment of the gate to the source and drain ohmic contacts, a gate-source and gate-drain spacing of 1-2 microns is typically used, resulting in a high parasitic resistance there. This parasitic resistance can severely limit speed performance in digital logic integrated circuits.
The task of minimizing the gate-source and gate-drain parasitic resistances is alleviated, to some degree, by the prior art technique known as the self-aligned gate process. An example of this prior art process consists of fabricating titanium-tungsten (TiW) gates, and using them as self-aligned masks to implant a heavily doped (n+) region on both sides of the gate.
The implanted GaAs wafer with the TiW gates on it is then annealed to activate the n+ implant, with the result that the .about.13 k.OMEGA./.quadrature. of the ungated FET channel is reduced to the .about.150 .OMEGA./.quadrature. of the self-aligned n+ implant. In the prior art process, the spacing between the gate and the source and drain contacts is still limited by alignment tolerances. The use of TiW for the gate metal is necessary to maintain the integrity of the Schottky gate contact during the high-temperature (800.degree. C.) anneal of the n+ implant. Therefore the prior art self-aligned gate process, is inadequate by itself to completely minimize parasitic resistances.
The task of minimizing the gate-source and gate-drain parasitic resistances and their effects is further alleviated by the following prior art patents:
U.S. Pat. No. 4,319,395 issued to Lund et al on Mar. 16, 1982; PA1 U.S. Pat. No. 4,182,023 issued to Cohen et al on Jan. 8, 1980; PA1 U.S. Pat. No. 4,141,022 issued to Sigg et al on Feb. 20, 1979; and PA1 U.S. Pat. No. 4,033,797 issued to Dill et al on July 5, 1977.
The Lund et al, Cohen et al, Sigg et al and Dill et al patents, incorporated herein by reference, all disclose a "mushroom" gate construction. The "mushroom" gate has been used for controlled shortening of gate lengths, but there remains the need for a device and process that will both combine the mushroom gate construction with the self-aligned gate process, as well as select specific materials which are compatible with GaAs MESFET in which the Schottky gate is able to withstand high implant-annealing temperatures of 800.degree.-850.degree. C. The present invention is directed towards satisfying that need.